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The CANopenIA-M0 SoM implements the CANopen protocol compliant to the CiA standards.CANopenIA-M0 is based on the NXP Cortex M0 32-bit micro controller. A derivative with integrated CAN transceiver is used to minimize the external components needed around the protocol chip. The Cortex architecture in conjunction with the optimized firmware design results in a very high performance. Time delays between in our outgoing CAN PDOs and hardware events are brought down to 15 micro seconds.
This high performant and ready to use CANopen solution is available as a chip or as a module. The module implements around the chip the clock generation, a serial EEPROM to store the configuration data and two LEDs to signal the CANopen state. To become familiar with COIA-M0 a starter kit and evaluation kit is available.
Entries in the object dictionary, the I/O ports and the SDO and PDO behavior is configured with a straightforward setup tool.
Features
CANopenIA-M0 Setup Utility
With the CANopenIA-M0 Setup utility all features supported by the CANopenIA-M0 chip are configured in a very easy manner. The setup utility generates a data set to be downloaded to the chip and a device configuration file which can be read by third party CANopen configuration tools.
For configuration and test any PEAK PCAN-USB PC interface is required.
For testing a CANopen Monitor such as CANopen Magic should be used.
Documents
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